Yingxue Gao

Yingxue Gao

Associate Professor at Nanjing University of Posts and Telecommunications (NJUPT)

Biography

I am an associate professor with the School of Integrated Circuit Science and Engineering at Nanjing University of Posts. Previously, I received the Ph.D. degree in Computer Science and Technology from the University of Science and Technology of China (USTC) in June 2025 and the B.S. degree in Computer Science and Technology from the Dalian University of Technology (DLUT) in June 2020. My research interests include FPGA Accelerator Design, Accelerator Design for Security, Advanced Cryptographic Hardware Acceleration, Post-Quantum Cryptographic Hardware Acceleration, and AI Hardware Acceleration. I serve as an Executive Committee Member of the CCF Fault-Tolerant Computing Technical Committee.

Research Interests

• FPGA Accelerator Design
• Advanced Cryptographic Hardware Acceleration
• Post-Quantum Cryptographic Hardware Acceleration
• AI Hardware Acceleration

Education & Work Experience

• Associate Professor in Nanjing University of Posts and Telecommunications (NJUPT), Nanjing, China, Since 2025
• Ph.D. in University of Science and Technology of China (USTC), Hefei, China, 2025
• B.S. in Dalian University of Technology (DLUT), Dalian, China, 2020

Publications

[1] Yingxue Gao, et al, “Enhancing Kyber Acceleration in Post-Quantum Cryptography through Configurable Hardware Architecture and Efficient Dataflow Mapping”, in IEEE Transactions on Computers. (Submitted).

[2] Yingxue Gao, Teng Wang, Yang Yang, Lei Gong, Xianglan Chen, Chao Wang, Xi Li, Xuehai Zhou, “Advancing Neuromorphic Architecture Towards Emerging Spiking Neural Network on FPGA”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 3465-3478, Sep. 2025. (TCAD’2025, CCF-A).

[3] Yingxue Gao, Teng Wang, Lei Gong, Chao Wang, Dong Dai, Yang Yang, Xianglan Chen, Xi Li and Xuehai Zhou, “Hardware Accelerated Vision Transformer via Heterogeneous Architecture Design and Adaptive Dataflow Mapping,” in IEEE Transactions on Computers, pp. 1224-1238, Apr. 2025. (TC’2025, CCF-A).

[4] Yingxue Gao, Teng Wang, Lei Gong, Chao Wang, Yiqing Hu, Yi Yang, Zhongming Liu, Xi Li, Xuehai Zhou, “Enhancing Graph Random Walk Acceleration via Efficient Dataflow and Hybrid Memory Architecture, “ in IEEE Transactions on Computers, pp. 887-901, Mar. 2024. (TC’2024, CCF-A).

[5] Yingxue Gao, Lei Gong, Chao Wang, Teng Wang, Xi Li and Xuehai Zhou, “Algorithm/Hardware Co-optimization for Sparsity-Aware SpMM Acceleration of GNNs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 4763-4776, Dec. 2023. (TCAD’2023, CCF-A).

[6] Yingxue Gao, Teng Wang, Lei Gong, Chao Wang, Xi Li and Xuehai Zhou, “FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAs,” Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6. (DATE’2023, CCF-B).

[7] Yingxue Gao, Lei Gong, Chao Wang and Xuehai Zhou, “Work-in-Progress: HeteroRW: A Generalized and Efficient Framework for Random Walks in Graph Analysis,” International Conference on Hardware/Software Codesign and System Synthesis, pp. 9-10. (CODES+ISSS’2022, CCF-B).

[8] Yingxue Gao, Lei Gong, Chao Wang, Teng Wang and Xuehai Zhou, “SDMA: An Efficient and Flexible Sparse-Dense Matrix-Multiplication Architecture for GNNs,” International Conference on Field-Programmable Logic and Applications, pp. 307-312. (FPL’2022, CCF-C).

[9] Teng Wang, Lei Gong, Chao Wang, Yang Yang, Yingxue Gao, Xuehai Zhou, Huaping Chen, “Via: A novel vision-transformer accelerator based on fpga”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 4088-4099, Nov. 2022. (TCAD’2022, CCF-A).

[10] Yang Yang, Chao Wang, Lei Gong, Min Wu, Zhenghua Chen, Yingxue Gao, Teng Wang, Xuehai Zhou, “Uncertainty-Aware Self-Knowledge Distillation”, in IEEE Transactions on Circuits and Systems for Video Technology, pp. 4464-4478, May 2025. (TCSVT’2025, CCF-B)

[11] Teng Wang, Lei Gong, Chao Wang, Yang Yang, Yingxue Gao, “Multi-clusters: An Efficient Design Paradigm of NN Accelerator Architecture Based on FPGA”, IFIP International Conference on Network and Parallel Computing, pp. 143-154. (NPC’2022, CCF-C)

Reviewer

• IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
• IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
• IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB)
• Frontiers of Information Technology & Electronic Engineering (FITEE, T1)
• International Journal of Electronics
• Microprocessors and Microsystems
• IET Computers & Digital Techniques

Award

• The 2025 CCF Incentive Program for Outstanding Doctoral Dissertations in Integrated Circuit Design, CCF Integrated Circuit Design and Automation Technical Committee

Services

• Technical Program Committee (TPC), Design Automation Conference (DAC, Top Conference in EDA and Design)
• Executive Committee Member, CCF Fault-Tolerant Computing Technical Committee
• Forum Chair, 2025 CCF 6th Conference on Integrated Circuits Design and Automation (CCFDAC) (“Advanced Cryptography Hardware Acceleration”)
• Student Chair, 2025 CCF 21st National Conference on Fault-Tolerant Computing

Correspondence

• Email: gyingxue@njupt.edu.cn
• Address: Xianlin Campus: 163 Xianlin Road, Qixia District, Nanjing, Jiangsu Province, 210023